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1 for more information www.analog.com typical application features description 42 v , 1.5 a synchronous step - down regulator with 2.5 a quiescent current the lt ? 860 8 is a compact , high efficiency , high speed synchronous monolithic step - down switching regulator that consumes only 1.7 a of quiescent current . the lt 8608 can deliver 1.5 a of continuous current . low ripple burst mode operation enables high efficiency down to very low output currents while keeping the output ripple below 10 mv . internal compensation with peak current mode topology allows the use of small inductors and results in fast transient response and good loop stability . the en / uv pin has an accurate 1 v threshold and can be used to program v in undervoltage lockout or to shut down the lt 8608 . the pg flag signals when v out is within 8.5% of the programmed output voltage as well as fault conditions . the msop package includes a sync pin to synchronize to an external clock , or to select burst mode operation or ? pulse - skipping with or without spread - spectrum ; the tr / ss pin programs soft - start or tracking . the dfn package omits these pins and can be purchased in pulse - skipping or burst mode operation varieties . package sync functionality lt 8608 mse mse programmable lt 8608 dfn dfn burst mode operation lt 8608 bdfn dfn pulse - skipping mode applications n wide input voltage range: 3.0v to 42v n ultralow quiescent current burst mode ? operation: n <2.5a i q regulating 12v in to 3.3v out n output ripple <10mv p-p n high effciency 2mhz synchronous operation: n >92% effciency at 0.5a, 5v out from 12v in n 1.5a continuous output current n fast minimum switch-on time: 35ns n adjustable and synchronizable: 200khz to 2.2mhz n spread spectrum frequency modulation for low emi n allows use of small inductors n low dropout n peak current mode operation n accurate 1v enable pin threshold n internal compensation n output soft-start and tracking n small 10-lead msop package or 8-lead 2mm? ?2mm dfn package n general purpose step down n low emi step down all registered trademarks and trademarks are the property of their respective owners . 5 v , 2 mhz step - down 12 v in to 5 v out efficiency c cc r r document feedback lt 8608 / lt 8608 b rev c 1.50 50 55 60 65 70 75 80 85 90 f sw = 2mhz 95 100 efficiency (%) in out 8608 ta01b i out (a) 0 0.25 0.50 0.75 1.00 1.25
2 for more information www.analog.com pin configuration absolute maximum ratings v in , en / uv , pg .......................................................... 42 v fb , tr / ss . ................................................................. 4 v sync voltage . ............................................................ 6 v ( note 1) cc r c r c c c c c r c top view bst sw intv cc rt en/uv v in pg fb dc package 8-lead (2mm 2mm) plastic dfn 9 gnd 4 1 2 3 6 5 7 8 order information lead free finish tape and reel part marking * package description temperature range lt 8608 emse # pbf lt 8608 emse # trpbf ltgvz 10- lead plastic msop C40 c to 125 c lt 8608 imse # pbf lt 8608 imse # trpbf ltgvz 10- lead plastic msop C40 c to 125 c lt 8608 hmse # pbf lt 8608 hmse # trpbf ltgvz 10- lead plastic msop C40 c to 150 c lt 8608 edc # pbf lt 8608 edc # trpbf lgxb 8- lead (2 mm = 2 mm ) plastic dfn C40 c to 125 c lt 8608 idc # pbf lt 8608 idc # trpbf lgxb 8- lead (2 mm = 2 mm ) plastic dfn C40 c to 125 c lt 8608 hdc # pbf lt 8608 hdc # trpbf lgxb 8- lead (2 mm = 2 mm ) plastic dfn C40 c to 150 c lt 8608 bedc # pbf lt 8608 bedc # trpbf lgxc 8- lead (2 mm = 2 mm ) plastic dfn C40 c to 125 c lt 8608 bidc # pbf lt 8608 bidc # trpbf lgxc 8- lead (2 mm = 2 mm ) plastic dfn C40 c to 125 c lt 8608 bhdc # pbf lt 8608 bhdc # trpbf lgxc 8- lead (2 mm = 2 mm ) plastic dfn C40 c to 150 c consult adi marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . for more information on lead free part marking , go to : http :// www . linear . com / leadfree / for more information on tape and reel specifications , go to : http :// www . linear . com / tapeandreel / . some packages are available in 500 unit reels through designated sales channels with # trmpbf suffix . electrical characteristics the l denotes the specifications which apply over the full operating temperature range , otherwise specifications are at t a = 25 c . http :// www . linear . com / product / lt 8608 # orderinfo parameter conditions min typ max units minimum input voltage l 2.5 3.0 3.2 v v in quiescent current v en / uv = 0 v , v sync = 0 v v en / uv = 2 v , not switching , v sync = 0 v or lt 8608 dfn , v in 36 v l 1 1.7 4 12 a a v in current in regulation v in = 6 v , v out = 2.7 v , output load = 100 a v in = 6 v , v out = 2.7 v , output load = 1 ma l l 56 500 90 700 a a operating junction temperature range ( note 2) lt 8608 e ........................................... C40 c to 125 c lt 8608 i ............................................. C40 c to 125 c lt 8608 h ............................................ C40 c to 150 c storage temperature range .................. C65 c to 150 c lt 8608 / lt 8608 b rev c
3 for more information www.analog.com electrical characteristics the l denotes the specifications which apply over the full operating temperature range , otherwise specifications are at t a = 25 c . note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device . exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime . absolute maximum ratings are those values beyond which the life of a device may be impaired . note 2: the lt 8608 e is guaranteed to meet performance specifications from 0 c to 125 c junction temperature . specifications over the C40 c to 125 c operating junction temperature range are assured by design , characterization , and correlation with statistical process controls . the lt 8608 i is guaranteed over the full C40 c to 125 c operating junction temperature range . the lt 8608 h is guaranteed over the full C40 c to 150 c operating junction temperature range . high junction temperatures degrade operating lifetimes . operating lifetime is derated at junction temperatures greater than 125 c . note 3: this ic includes overtemperature protection that is intended to protect the device during overload conditions . junction temperature will exceed 150 c when overtemperature protection is active . continuous operation above the specified maximum operating junction temperature will reduce lifetime . parameter conditions min typ max units feedback reference voltage msop package v in = 6 v , i load = 100 ma v in = 6 v , i load = 100 ma l 0.774 0.762 0.778 0.778 0.782 0.798 v v dfn package v in = 6 v , i load = 100 ma v in = 6 v , i load = 100 ma l 0.773 0.753 0.778 0.778 0.783 0.803 v v feedback voltage line regulation v in = 4.0 v to 40 v l 0.02 0.06 %/ v feedback pin input current v fb = 1 v l 20 na minimum on - time i load = 1 a , sync = 0 v or lt 8608 dfn i load = 1 a , sync = 1.9 v or lt 8608 b dfn l l 35 35 65 60 ns ns minimum off time 93 130 ns oscillator frequency msop package r t = 221 k , i load = 500 ma r t = 60.4 k , i load = 500 ma r t = 18.2 k , i load = 200 ma l l l 155 640 1.90 200 700 2.00 245 760 2.10 khz khz mhz dfn package r t = 221 k , i load = 500 ma r t = 60.4 k , i load = 500 ma r t = 18.2 k , i load = 200 ma l l l 130 610 1.85 200 700 2.00 270 790 2.15 khz khz mhz top power nmos on - resistance i load = 0.5 a 350 m top power nmos current limit l 2.1 2.9 3.9 a bottom power nmos on - resistance 230 m sw leakage current v in = 36 v l 15 a en / uv pin threshold en / uv rising l 0.99 1.05 1.11 v en / uv pin hysteresis 50 mv en / uv pin current v en / uv = 2 v l 20 na pg upper threshold offset from v fb v fb rising l 5.0 8.5 13.0 % pg lower threshold offset from v fb v fb falling l 5.0 8.5 13.0 % pg hysteresis 0.5 % pg leakage v pg = 42 v l 200 na pg pull - down resistance v pg = 0.1 v 550 1200 sync low input voltage msop only l 0.4 0.9 v sync high input voltage intv cc = 3.5 v , msop only l 2.7 3.2 v tr / ss source current msop only l 1 2 3 a tr / ss pull - down resistance fault condition , tr / ss = 0.1 v , msop only 300 900 spread spectrum modulation frequency v sync = 3.3 v , msop only l 0.5 3 6 khz lt 8608 / lt 8608 b rev c
4 for more information www.analog.com typical performance characteristics no - load supply current vs temperature efficiency (5 v output , burst mode operation ) efficiency (3.3 v output , 2 mhz , burst mode operation ) efficiency (3.3 v output , 2 mhz , burst mode operation ) fb voltage load regulation line regulation no - load supply current (3.3 v output ) efficiency (5 v output , burst mode operation ) sync = 0v or lt8608 dfn sync = 0v or lt8608 dfn sync = 0v or lt8608 dfn sync = 0v or lt8608 dfn sync = 0v or lt8608 dfn sync = 0v or lt8608 dfn lt 8608 / lt 8608 b rev c 50 0.50 0.75 1 1.25 1.50 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 55 0.0 0.1 0.2 0.3 0.4 0.5 change in v out (%) load regulation 8608g06 input voltage (v) 60 2 10 18 26 34 42 ?0.20 ?0.15 ?0.10 ?0.05 65 0.00 0.05 0.10 0.15 0.20 change in v out (%) 8608 g07 input voltage (v) 2 10 70 18 26 34 42 2.00 2.25 2.50 2.75 3.00 3.25 75 3.50 3.75 4.00 i in (a) (3.3v output) 8608 g08 temperature (c) ?50 ?10 30 80 70 110 150 1.3 1.5 1.7 1.9 2.1 2.3 2.5 85 2.7 2.9 3.1 3.3 input current (a) (not switching) 8608 g09 v in = 12v v in = 24v i out (ma) 90 0.001 0.01 0.1 1 10 100 1k 10k 0 10 95 20 30 40 50 60 70 80 90 100 efficiency (%) i out (a) 100 mode operation) 8608 g02 f sw = 2mhz l = 2.2h efficiency (%) mode operation) 8608 g01 l = 2.2h f sw = 2mhz v in = 12v v in = 24v f sw = 2mhz v in = 12v 0.00 v in = 24v l = 2.2h i out (a) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 0.25 50 55 60 65 70 75 80 85 90 95 0.50 100 efficiency (%) mode operation) 8608 g03 f sw = 2mhz v in = 12v v in = 24v l = 2.2h i out (ma) 0.001 0.75 0.01 0.1 1 10 100 1k 10k 0 10 20 1.00 30 40 50 60 70 80 90 100 efficiency (%) mode operation) 1.25 8608 g04 temperature (c) ?50 ?10 30 70 110 150 775 776 1.50 777 778 779 780 fb regulation voltage (mv) fb voltage 8608 g05 output current (a) 0 0.25
5 for more information www.analog.com typical performance characteristics top fet current limit vs duty cycle top fet current limit vs temperature switch drop vs temperature switch drop vs switch current minimum on - time vs temperature minimum off - time vs temperature dropout voltage vs load current burst frequency vs load current switching frequency vs temperature sync = 0v or lt8608 dfn lt 8608 / lt 8608 b rev c 30 8608 g15 l = xfl4020?222mec load current (a) 0 0.25 0.50 0.75 1 1.25 1.50 50 1.75 2 0 125 250 375 500 625 750 dropout voltage (mv) 70 dropout voltage vs load current 8608 g16 v out = 3.3v r t = 18.2k temperature (c) ?50 ?10 30 70 110 90 150 1975 1980 1985 1990 1995 2000 2005 2010 2015 110 2020 2025 swithcing frequency (khz) switching frequency vs temperature 8608 g17 load current (ma) 0 100 200 300 130 400 500 0 250 500 750 1000 1250 1500 1750 150 2000 2250 2500 swithcing frequency (khz) burst frequency vs load current 8608 g18 v in = 12v l = 2.2h v out = 3.3v duty cycle (%) 200 0 20 40 60 80 100 2.00 2.25 2.50 2.75 250 3.00 3.25 top fet current limit (a) top fet current limit vs duty cycle 8608 g10 duty cycle = 0 temperature (c) ?50 ?10 30 300 70 110 150 2.5 2.6 2.7 2.8 2.9 3.0 3.1 switch current = 1a 350 i sw (a) top fet current limit vs temperature 8608 g11 400 450 500 550 switch drop (mv) switch drop vs temperature 8608 g12 top sw bot sw top sw switch current (a) 0 0.25 0.50 0.75 1 1.25 1.50 1.75 2 bot sw 0 100 200 300 400 500 600 700 800 switch drop (mv) temperature (c) switch drop vs switch current 8608 g13 i out = 1a temperature (c) ?50 ?30 ?10 10 30 50 ?50 70 90 110 130 150 30 31 32 33 34 ?30 35 36 37 38 39 40 minimum on-time (ns) minimum on-time vs temperature 8608 g14 temperature (c) ?10 ?50 ?30 ?10 10 30 50 70 90 110 130 10 150 80 85 90 95 100 105 110 minimum off-time (ns) minimum off-time vs temperature
6 for more information www.analog.com typical performance characteristics minimum load to full frequency ( sync float to 1.9 v ) ( msop package ) frequency foldback soft - start tracking ( msop package ) steady state case temperature rise vs load current (5 v out ) soft - start current vs temperature ( msop package ) steady state case temperature rise vs load (3.3 v out ) v in uvlo start - up dropout start - up dropout sync = 0v or lt8608 dfn lt 8608 / lt 8608 b rev c 35 8608 g22 temperature (c) ?50 ?30 ?10 10 30 50 70 90 40 110 130 150 2.00 2.25 2.50 2.75 3.00 3.25 v in uvlo (v) 0 v in uvlo 8608 g23 v in = 6v v in = 12v v in = 36v i out (a) 0.00 0.25 0.50 0.75 25 1.00 1.25 1.50 0 5 10 15 20 25 30 50 35 40 45 50 case temp rise (c) (5v out) 8608 g24 f sw = 2mhz l = 2.2h f sw = 2mhz 75 l = 2.2h v in = 12v v in = 36v i out (a) 0.00 0.25 0.50 0.75 1.00 1.25 100 1.50 0 5 10 15 20 25 30 35 40 125 45 50 case temp rise (c) 8608 g25 r load = 50 input voltage (v) 0 1 2 3 load current (ma) 4 5 6 7 0 1 2 3 4 5 8608 g19 6 7 0 1 2 3 4 5 6 7 input voltage (v) l = 2.2h input voltage (v) output voltage (v) start?up droupout 8608 g26 v in v out v in v out r load = 5 input voltage (v) v out = 5v 0 1 2 3 4 5 6 7 0 1 r t = 18.2k 2 3 4 5 6 7 0 1 2 3 fb voltage (v) 4 5 6 7 input voltage (v) output voltage (v) start-up droupout 8608 027 0.0 0.1 0.2 0.3 0.4 0.5 0 0.6 0.7 0.8 0.9 1.0 r t = 18.2k 0 250 500 750 5 1000 1250 1500 1750 2000 2250 2500 frequency (khz) 8608 g20 ss voltage (v) 10 0 0.1 0.2 0.4 0.5 0.6 0.7 0.8 1.0 1.1 15 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 20 0.9 1.0 fb voltage (v) soft-start tracking 8608 g21 temperature (c) ?50 ?30 ?10 10 25 30 50 70 90 110 130 150 1.5 1.6 1.7 30 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 soft-start current (a) soft start current vs temperature
7 for more information www.analog.com typical performance characteristics switching waveforms switching waveforms transient response transient response switching waveforms 200ns/div 12v in to 3.3 v out at 1a 2mhz 10s/div 12v in to 5v out at 3ma 200ns/div 36v in to 3.3v out at 1a 2mhz lt 8608 / lt 8608 b rev c 8608 g32 v in = 24v 0.5a to 1a c out = 47 f f sw = 2mhz i l 1a/div sw 5v/div 8608 g28 i l 200ma/div sw 5v/div 8608 g29 i l 1a/div sw 2v/div 50s/div 8608 g30 i load 500ma/div v out 50mv/div 8608 g31 v in = 12v 0.5a to 1a c out = 47 f f sw = 2mhz 50s/div i load 500ma/div v out 50mv/div
8 for more information www.analog.com pin functions bst : this pin is used to provide a drive voltage , higher than the input voltage , to the topside power switch . place a 0.1 f boost capacitor as close as possible to the ic . do not place a resistor in series with this pin . sw : the sw pin is the output of the internal power switches . connect this pin to the inductor and boost capacitor . this node should be kept small on the pcb for good performance . intv cc : internal 3.5 v regulator bypass pin . the internal power drivers and control circuits are powered from this voltage . intv cc max output current is 20 ma . voltage on intv cc will vary between 2.8 v and 3.5 v . decouple this pin to power ground with at least a 1 f low esr ceramic capacitor . do not load the intv cc pin with external circuitry . rt : a resistor is tied between rt and ground to set the switching frequency . when synchronizing , the r t resistor should be chosen to set the lt 8608 switching frequency equal to or below the lowest synchronization input . sync ( msop only ): external clock synchronization input . ground this pin for low ripple burst mode operation at low output loads . tie to a clock source for synchronization to an external frequency . leave floating for pulse - skipping mode with no spread spectrum modulation . tie to intv cc or tie to a voltage between 3.2 v and 5.0 v for pulse - skipping mode with spread spectrum modulation . when in pulse - skipping mode , the i q will increase to several ma . there is no sync pin in the lt 8608 dfn package . the lt 8608 dfn package internally ties sync to ground . the lt 8608 b dfn package internally floats sync . fb : the lt 8608 regulates the fb pin to 0.778 v . connect the feedback resistor divider tap to this pin . tr / ss ( msop only ): output tracking and soft - start pin . this pin allows user control of output voltage ramp rate during start - up . a tr / ss voltage below 0.778 v forces the lt 8608 to regulate the fb pin to equal the tr / ss pin volt - age . when tr / ss is above 0.778 v , the tracking function is disabled and the internal reference resumes control of the error amplifier . an internal 2 a pull - up current from intv cc on this pin allows a capacitor to program output voltage slew rate . this pin is pulled to ground with a 300 mosfet during shutdown and fault conditions ; use a series resistor if driving from a low impedance output . there is no tr / ss pin in the lt 8608 dfn or lt 8608 b and the node is internally floated . pg : the pg pin is the open - drain output of an internal comparator . pg remains low until the fb pin is within 8.5% of the final regulation voltage , and there are no fault conditions . pg is valid when v in is above 3.2 v , regardless of en / uv pin state . v in : the v in pin supplies current to the lt 8608 internal circuitry and to the internal topside power switch . this pin must be locally bypassed . be sure to place the positive terminal of the input capacitor as close as possible to the v in pins , and the negative capacitor terminal as close as possible to the gnd pins . en / uv : the lt 8608 is shut down when this pin is low and active when this pin is high . the hysteretic threshold volt - age is 1.05 v going up and 1.00 v going down . tie to v in if the shutdown feature is not used . an external resistor divider from v in can be used to program a v in threshold below which the lt 8608 will shut down . gnd : exposed pad pin . the exposed pad must be con - nected to the negative terminal of the input capacitor and soldered to the pcb in order to lower the thermal resistance . lt 8608 / lt 8608 b rev c
9 for more information www.analog.com block diagram + + ? + ? slope comp internal 0.778v ref oscillator 200khz to 2.2mhz burst detect 3.5v reg m1 m2 c bst c out v out 8608 bd sw l bst switch logic and anti- shoot through error amp shdn 8.5% v c shdn tsd intv cc uvlo v in uvlo shdn tsd v in uvlo en/uv r3 (opt) r4 (opt) 1v + ? intv cc gnd pg fb r1 r2 r t c ss v out r pg c ff tr/ss 2a rt sync v in v in c in c vcc lt 8608 / lt 8608 b rev c
10 for more information www.analog.com operation the lt 8608 is a monolithic constant frequency current mode step - down dc / dc converter . an oscillator with frequency set using a resistor on the rt pin turns on the internal top power switch at the beginning of each clock cycle . current in the inductor then increases until the top switch current comparator trips and turns off the top power switch . the peak inductor current at which the top switch turns off is controlled by the voltage on the internal vc node . the error amplifier servos the vc node by comparing the voltage on the v fb pin with an internal 0.778 v reference . when the load current increases it causes a reduction in the feedback voltage relative to the reference leading the error amplifier to raise the vc volt - age until the average inductor current matches the new load current . when the top power switch turns off the synchronous power switch turns on until the next clock cycle begins or inductor current falls to zero . if overload conditions result in excess current flowing through the bottom switch , the next clock cycle will be delayed until switch current returns to a safe level . if the en / uv pin is low , the lt 8608 is shut down and draws 1 a from the input . when the en / uv pin is above 1.05 v , the switching regulator becomes active . to optimize efficiency at light loads , the lt 8608 enters burst mode operation during light load situations . between bursts , all circuitry associated with controlling the output switch is shut down , reducing the input supply current to 1.7 a . in a typical application , 2.5 a will be consumed from the input supply when regulating with no load . the sync pin is tied low to use burst mode operation and can be floated to use pulse - skipping mode . if a clock is applied to the sync pin the part will synchronize to an external clock frequency and operate in pulse - skipping mode . while in pulse - skipping mode the oscillator oper - ates continuously and positive sw transitions are aligned to the clock . during light loads , switch pulses are skipped to regulate the output and the quiescent current will be several ma . the sync pin may be tied high for spread spectrum modulation mode , and the lt 8608 will oper - ate similar to pulse - skipping mode but vary the clock frequency to reduce emi . the lt 8608 dfn has no sync pin and will always operate in burst mode operation . the lt 8608 b dfn has no sync pin and will always operate in pulse - skipping mode . comparators monitoring the fb pin voltage will pull the pg pin low if the output voltage varies more than 8.5% ( typical ) from the set point , or if a fault condition is present . the oscillator reduces the lt 8608 s operating frequency when the voltage at the fb pin is low . this frequency fold - back helps to control the inductor current when the output voltage is lower than the programmed value which occurs during start - up . when a clock is applied to the sync pin the frequency foldback is disabled . applications information achieving ultralow quiescent current to enhance efficiency at light loads , the lt 8608 enters into low ripple burst mode operation , which keeps the output capacitor charged to the desired output voltage while minimizing the input quiescent current and minimizing output voltage ripple . in burst mode operation the lt 8608 delivers single small pulses of current to the output capaci - tor followed by sleep periods where the output power is supplied by the output capacitor . while in sleep mode the lt 8608 consumes 1.7 a . as the output load decreases , the frequency of single cur - rent pulses decreases ( see figure 1 ) and the percentage of time the lt 8608 is in sleep mode increases , resulting in much higher light load efficiency than for typical convert - ers . by maximizing the time between pulses , the converter quiescent current approaches 2.5 a for a typical application when there is no output load . therefore , to optimize the quiescent current performance at light loads , the current in the feedback resistor divider must be minimized as it appears to the output as load current . lt 8608 / lt 8608 b rev c
11 for more information www.analog.com applications information figure 2. full switching frequency minimum load vs v in in pulse skipping mode ( msop only ) figure 1. sw burst mode frequency vs load for some applications it is desirable for the lt 8608 to operate in pulse - skipping mode , offering two major differ - ences from burst mode operation . first is the clock stays awake at all times and all switching cycles are aligned to the clock . in this mode much of the internal circuitry is awake at all times , increasing quiescent current to several hundred a . second is that full switching frequency is reached at lower output load than in burst mode operation as shown in figure 2 . to enable pulse - skipping mode the sync pin is floated . to achieve spread spectrum modula - tion with pulse - skipping mode , the sync pin is tied high . while a clock is applied to the sync pin the lt 8608 will also operate in pulse - skipping mode . the lt 8608 dfn is programmed for burst mode operation and can not enter pulse - skipping mode . the lt 8608 b dfn is programmed for pulse - skipping and cannot enter burst mode operation . while in burst mode operation the current limit of the top switch is approximately 550 ma resulting in output voltage ripple shown in figure 3 and figure 4 . increasing the output capacitance will decrease the output ripple proportionally . as load ramps upward from zero the switch - ing frequency will increase but only up to the switching frequency programmed by the resistor at the rt pin as shown in figure 1 . the output load at which the lt 8608 reaches the programmed frequency varies based on input voltage , output voltage , and inductor choice . figure 4. burst mode operation ( zoomed in ) figure 3. burst mode operation 20s/div 500ns/div lt 8608 / lt 8608 b rev c 250 500 750 1000 1250 1500 1750 2000 2250 2500 load current (ma) swithcing frequency (khz) burst frequency vs load current 8608 f01 v in = 12v l = 2.2h v out = 3.3v sync = 0v input voltage (v) 0 5 0 10 15 20 25 30 35 40 0 25 50 100 75 100 125 load current (ma) 8608 f02 l = 2.2h v out = 5v r t = 18.2k v out 20mv/div inductor current 500ma/div 200 8608 f03 sw 5v/div v out 20mv/div inductor current 500ma/div 8608 f04 sw 5v/div 300 400 500 0
12 for more information www.analog.com applications information fb resistor network the output voltage is programmed with a resistor divider between the output and the fb pin . choose the resistor values according to : r 1 = r 2 v o u t 0 . 7 7 8 v C 1 ? ? ? ? ? ? 1% resistors are recommended to maintain output volt - age accuracy . the total resistance of the fb resistor divider should be selected to be as large as possible when good low load efficiency is desired : the resistor divider generates a small load on the output , which should be minimized to optimize the quiescent current at low loads . when using large fb resistors , a 10 pf phase lead capacitor should be connected from v out to fb . setting the switching frequency the lt 8608 uses a constant frequency pwm architecture that can be programmed to switch from 200 khz to 2.2 mhz by using a resistor tied from the rt pin to ground . a table showing the necessary r t value for a desired switching frequency is in table 1. when in spread spectrum modu - lation mode , the frequency is modulated upwards of the frequency set by r t . table 1. sw frequency vs rt value f sw ( mhz ) r t ( k ) 0.2 221 0.300 143 0.400 110 0.500 86.6 0.600 71.5 0.700 60.4 0.800 52.3 0.900 46.4 1.000 40.2 1.200 33.2 1.400 27.4 1.600 23.7 1.800 20.5 2.000 18.2 2.200 16.2 operating frequency selection and trade - offs selection of the operating frequency is a trade - off between efficiency , component size , and input voltage range . the advantage of high frequency operation is that smaller induc - tor and capacitor values may be used . the disadvantages are lower efficiency and a smaller input voltage range . the highest switching frequency ( f sw ( max ) ) for a given application can be calculated as follows : f s w ( m a x ) = v o u t + v s w ( b o t ) t o n ( m i n ) v i n C v s w ( t o p ) + v s w ( b o t ) ( ) where v in is the typical input voltage , v out is the output voltage , v sw ( top ) and v sw ( bot ) are the internal switch drops (~0.55 v , ~0.35 v , respectively at max load ) and t on ( min ) is the minimum top switch on - time ( see electrical characteristics ). this equation shows that slower switch - ing frequency is necessary to accommodate a high v in / v out ratio . for transient operation v in may go as high as the abs max rating regardless of the rt value , however the lt 8608 will reduce switching frequency as necessary to maintain control of inductor current to assure safe operation . the lt 8608 is capable of maximum duty cycle approach - ing 100%, and the v in to v out dropout is limited by the r ds ( on ) of the top switch . in this mode the lt 8608 skips switch cycles , resulting in a lower switching frequency than programmed by r t . for applications that cannot allow deviation from the pro - grammed switching frequency at low v in / v out ratios use the following formula to set switching frequency : v i n ( m i n ) = v o u t + v s w ( b o t ) 1 C f s w ? t o f f ( m i n ) C v s w ( b o t ) + v s w ( t o p ) where v in ( min ) is the minimum input voltage without skipped cycles , v out is the output voltage , v sw ( top ) and v sw ( bot ) are the internal switch drops (~0.55 v , ~0.35 v , respectively at max load ), f sw is the switching frequency ( set by rt ), and t off ( min ) is the minimum switch off - time . note that higher switching frequency will increase the minimum input voltage below which cycles will be dropped to achieve higher duty cycle . lt 8608 / lt 8608 b rev c
13 for more information www.analog.com applications information inductor selection and maximum output current the lt 8608 is designed to minimize solution size by al - lowing the inductor to be chosen based on the output load requirements of the application . during overload or short circuit conditions the lt 8608 safely tolerates operation with a saturated inductor through the use of a high speed peak - current mode architecture . a good first choice for the inductor value is : l = v o u t + v s w ( b o t ) f s w where f sw is the switching frequency in mhz , v out is the output voltage , v sw ( bot ) is the bottom switch drop (~0.35 v ) and l is the inductor value in h . to avoid overheating and poor efficiency , an inductor must be chosen with an rms current rating that is greater than the maximum expected output load of the application . in addition , the saturation current ( typically labeled i sat ) rat - ing of the inductor must be higher than the load current plus 1/2 of in inductor ripple current : i l ( p e a k ) = i l o a d ( m a x ) + 1 2 ? l where ? i l is the inductor ripple current as calculated several paragraphs below and i load ( max ) is the maximum output load for a given application . as a quick example , an application requiring 0.5 a output should use an inductor with an rms rating of greater than 0.5 a and an i sat of greater than 0.8 a . to keep the efficiency high , the series resistance ( dcr ) should be less than 0.04, and the core material should be intended for high frequency applications . the lt 8608 limits the peak switch current in order to protect the switches and the system from overload faults . the top switch current limit ( i lim ) is at least 2.1 a at low duty cycles and decreases linearly to 1.55 a at d = 0.8. the inductor value must then be sufficient to supply the desired maximum output current ( i out ( max ) ), which is a function of the switch current limit ( i lim ) and the ripple current : i o u t ( m a x ) = i l i m C ? i l 2 the peak - to - peak ripple current in the inductor can be calculated as follows : ? i l = v o u t l ? f s w 1 C v o u t v i n ( m a x ) ? ? ? ? ? ? ? ? where f sw is the switching frequency of the lt 8608 , and l is the value of the inductor . therefore , the maximum output current that the lt 8608 will deliver depends on the switch current limit , the inductor value , and the input and output voltages . the inductor value may have to be increased if the inductor ripple current does not allow sufficient maximum output current ( i out ( max ) ) given the switching frequency , and maximum input voltage used in the desired application . for more information about maximum output current and discontinuous operation , see analog device s application note 44. finally , for duty cycles greater than 50% ( v out / v in > 0.5), a minimum inductance is required to avoid sub - harmonic oscillation . see application note 19. input capacitor bypass the input of the lt 8608 circuit with a ceramic capaci - tor of x 7 r or x 5 r type . y 5 v types have poor performance over temperature and applied voltage , and should not be used . a 4.7 f to 10 f ceramic capacitor is adequate to bypass the lt 8608 and will easily handle the ripple current . note that larger input capacitance is required when a lower switching frequency is used . if the input power source has high impedance , or there is significant inductance due to long wires or cables , additional bulk capacitance may be necessary . this can be provided with a low performance electrolytic capacitor . step - down regulators draw current from the input sup - ply in pulses with very fast rise and fall times . the input capacitor is required to reduce the resulting voltage ripple at the lt 8608 and to force this very high frequency switching current into a tight local loop , minimizing emi . a 4.7 f capacitor is capable of this task , but only if it is placed close to the lt 8608 ( see the pcb layout section ). a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the lt 8608 . lt 8608 / lt 8608 b rev c
14 for more information www.analog.com applications information a ceramic input capacitor combined with trace or cable inductance forms a high quality ( under damped ) tank cir - cuit . if the lt 8608 circuit is plugged into a live supply , the input voltage can ring to twice its nominal value , possibly exceeding the lt 8608 s voltage rating . this situation is easily avoided ( see analog devices application note 88). output capacitor and output ripple the output capacitor has two essential functions . along with the inductor , it filters the square wave generated by the lt 8608 to produce the dc output . in this role it determines the output ripple , thus low impedance at the switching frequency is important . the second function is to store energy in order to satisfy transient loads and stabilize the lt 8608 s control loop . ceramic capacitors have very low equivalent series resistance ( esr ) and provide the best ripple performance . a good starting value is : c o u t = 1 0 0 v o u t ? f s w where f sw is in mhz , and c out is the recommended output capacitance in f . use x 5 r or x 7 r types . this choice will provide low output ripple and good transient response . transient performance can be improved with a higher value output capacitor and the addition of a feedforward capacitor placed between v out and fb . increasing the output capacitance will also decrease the output voltage ripple . a lower value of output capacitor can be used to save space and cost but transient performance will suffer and may cause loop instability . see the typical applications in this data sheet for suggested capacitor values . when choosing a capacitor , special attention should be given to the data sheet to calculate the effective capacitance under the relevant operating conditions of voltage bias and temperature . a physically larger capacitor or one with a higher voltage rating may be required . ceramic capacitors ceramic capacitors are small , robust and have very low esr . however , ceramic capacitors can cause problems when used with the lt 8608 due to their piezoelectric nature . when in burst mode operation , the lt 8608 s switching frequency depends on the load current , and at very light loads the lt 8608 can excite the ceramic capacitor at audio frequencies , generating audible noise . since the lt 8608 operates at a lower current limit during burst mode operation , the noise is typically very quiet to a casual ear . if this is unacceptable , use a high performance tantalum or electrolytic capacitor at the output . a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the lt 8608 . as pre - viously mentioned , a ceramic input capacitor combined with trace or cable inductance forms a high quality ( under damped ) tank circuit . if the lt 8608 circuit is plugged into a live supply , the input voltage can ring to twice its nominal value , possibly exceeding the lt 8608 s rating . this situation is easily avoided ( see analog devices ap - plication note 88). enable pin the lt 8608 is in shutdown when the en pin is low and active when the pin is high . the rising threshold of the en comparator is 1.05 v , with 50 mv of hysteresis . the en pin can be tied to v in if the shutdown feature is not used , or tied to a logic level if shutdown control is required . adding a resistor divider from v in to en programs the lt 8608 to regulate the output only when v in is above a desired voltage ( see block diagram ). typically , this threshold , v in ( en ) , is used in situations where the input supply is current limited , or has a relatively high source resistance . a switching regulator draws constant power from the source , so source current increases as source voltage drops . this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions . the v in ( en ) threshold prevents the regulator from operating at source voltages where the problems might occur . this threshold can be adjusted by setting the values r 3 and r 4 such that they satisfy the following equation : v i n ( e n ) = r 3 r 4 + 1 ? ? ? ? ? ? ? 1 v where the lt 8608 will remain off until v in is above v in ( en ) . due to the comparator s hysteresis , switching will not stop until the input falls slightly below v in ( en ) . lt 8608 / lt 8608 b rev c
15 for more information www.analog.com when in burst mode operation for light - load currents , the current through the v in ( en ) resistor network can easily be greater than the supply current consumed by the lt 8608 . therefore , the v in ( en ) resistors should be large to minimize their effect on efficiency at low loads . intv cc regulator an internal low dropout ( ldo ) regulator produces the 3.5 v supply from v in that powers the drivers and the internal bias circuitry . the intv cc can supply enough current for the lt 8608 s circuitry and must be bypassed to ground with a minimum of 1 f ceramic capacitor . good bypassing is necessary to supply the high transient currents required by the power mosfet gate drivers . applications with high input voltage and high switching frequency will increase die temperature because of the higher power dissipation across the ldo . do not connect an external load to the intv cc pin . output voltage tracking and soft - start ( msop only ) the lt 8608 allows the user to program its output voltage ramp rate by means of the tr / ss pin . an internal 2 a pulls up the tr / ss pin to intv cc . putting an external capaci - tor on tr / ss enables soft - starting the output to prevent current surge on the input supply . during the soft - start ramp the output voltage will proportionally track the tr / ss pin voltage . for output tracking applications , tr / ss can be externally driven by another voltage source . from 0 v to 0.778 v , the tr / ss voltage will override the internal 0.778 v reference input to the error amplifier , thus regulat - ing the fb pin voltage to that of tr / ss pin . when tr / ss is above 0.778 v , tracking is disabled and the feedback voltage will regulate to the internal reference voltage . an active pull - down circuit is connected to the tr / ss pin which will discharge the external soft - start capacitor in the case of fault conditions and restart the ramp when the faults are cleared . fault conditions that clear the soft - start capacitor are the en / uv pin transitioning low , v in voltage falling too low , or thermal shutdown . the lt 8608 and lt 8608 b dfn do not have tr / ss pin or functionality . output power good when the lt 8608 s output voltage is within the 8.5% window of the regulation point , which is a v fb voltage in the range of 0.716 v to 0.849 v ( typical ), the output voltage applications information is considered good and the open - drain pg pin goes high impedance and is typically pulled high with an external resistor . otherwise , the internal drain pull - down device will pull the pg pin low . to prevent glitching both the upper and lower thresholds include 0.5% of hysteresis . the pg pin is also actively pulled low during several fault conditions : en / uv pin is below 1 v , intv cc has fallen too low , v in is too low , or thermal shutdown . synchronization ( msop only ) to select low ripple burst mode operation , tie the sync pin below 0.4 v ( this can be ground or a logic low output ). to synchronize the lt 8608 oscillator to an external frequency connect a square wave ( with 20% to 80% duty cycle ) to the sync pin . the square wave amplitude should have val - leys that are below 0.9 v and peaks above 2.7 v ( up to 5 v ). the lt 8608 will not enter burst mode operation at low output loads while synchronized to an external clock , but instead will pulse skip to maintain regulation . the lt 8608 may be synchronized over a 200 khz to 2.2 mhz range . the r t resistor should be chosen to set the lt 8608 switching frequency equal to or below the lowest synchronization input . for example , if the synchronization signal will be 500 khz and higher , the r t should be selected for 500 khz . the slope compensation is set by the r t value , while the minimum slope compensation required to avoid subhar - monic oscillations is established by the inductor size , input voltage , and output voltage . since the synchroniza - tion frequency will not change the slopes of the inductor current waveform , if the inductor is large enough to avoid subharmonic oscillations at the frequency set by rt , then the slope compensation will be sufficient for all synchro - nization frequencies . for some applications it is desirable for the lt 8608 to operate in pulse - skipping mode , offering two major differ - ences from burst mode operation . first is the clock stays awake at all times and all switching cycles are aligned to the clock . second is that full switching frequency is reached at lower output load than in burst mode operation as shown in figure 2 in an earlier section . these two differences come at the expense of increased quiescent current . to enable pulse - skipping mode the sync pin is floated . lt 8608 / lt 8608 b rev c
16 for more information www.analog.com applications information for some applications , reduced emi operation may be desirable , which can be achieved through spread spectrum modulation . this mode operates similar to pulse skipping mode operation , with the key difference that the switching frequency is modulated up and down by a 3 khz triangle wave . the modulation has the frequency set by rt as the low frequency , and modulates up to approximately 20% higher than the frequency set by rt . to enable spread spectrum mode , tie sync to intv cc or drive to a voltage between 3.2 v and 5 v . the lt 8608 does not operate in forced continuous mode regardless of sync signal . the lt 8608 dfn is programmed for burst mode operation and cannot enter pulse skipping mode . the lt 8608 b dfn is programmed for pulse - skipping and cannot enter burst mode operation . shorted and reversed input protection the lt 8608 will tolerate a shorted output . several features are used for protection during output short - circuit and brownout conditions . the first is the switching frequency will be folded back while the output is lower than the set point to maintain inductor current control . second , the bottom switch current is monitored such that if inductor current is beyond safe levels switching of the top switch will be delayed until such time as the inductor current falls to safe levels . this allows for tailoring the lt 8608 to individual applications and limiting thermal dissipation during short circuit conditions . frequency foldback behavior depends on the state of the sync pin : if the sync pin is low or high , or floated the switching frequency will slow while the output voltage is lower than the programmed level . if the sync pin is connected to a clock source , the lt 8608 will stay at the programmed frequency without foldback and only slow switching if the inductor current exceeds safe levels . there is another situation to consider in systems where the output will be held high when the input to the lt 8608 is absent . this may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode ored with the lt 8608 s output . if the v in pin is allowed to float and the en pin is held high ( either by a logic signal or because it is tied to v in ), then the lt 8608 s internal circuitry will pull its quiescent current through its sw pin . this is acceptable if the system can tolerate several a in this state . if the en pin is grounded the sw pin current will drop to near 0.7 a . however , if the v in pin is grounded while the output is held high , re - gardless of en , parasitic body diodes inside the lt 8608 can pull current from the output through the sw pin and the v in pin . figure 5 shows a connection of the v in and en / uv pins that will allow the lt 8608 to run only when the input voltage is present and that protects against a shorted or reversed input . v in v in lt8608 gnd d1 8608 f05 en/uv figure 5. reverse v in protection pcb layout for proper operation and minimum emi , care must be taken during printed circuit board layout . figure 7 shows the recommended component placement with trace , ground plane and via locations . note that large , switched currents flow in the lt 8608 s v in pins , gnd pins , and the input capacitor ( c 1). the loop formed by the input capacitor should be as small as possible by placing the capacitor adjacent to the v in and gnd pins . when using a physically large input capacitor the resulting loop may become too large in which case using a small case / value capacitor placed close to the v in and gnd pins plus a larger capacitor further away is preferred . these components , along with the inductor and output capacitor , should be placed on the same side of the circuit board , and their connections should be made on that layer . place a local , unbroken ground plane under the application circuit on the layer closest to the surface layer . the sw and boost nodes should be as small as possible . finally , keep the fb and rt nodes small so that the ground traces will shield them from the sw and boost nodes . the exposed pad on the bottom of the package must be soldered to ground so that the pad is connected to ground electrically and also lt 8608 / lt 8608 b rev c
17 for more information www.analog.com applications information to ambient . the lt 8608 will stop switching and indicate a fault condition if safe junction temperature is exceeded . temperature rise of the lt 8608 is worst when operating at high load , high v in , and high switching frequency . if the case temperature is too high for a given application , then either v in , switching frequency or load current can be decreased to reduce the temperature to an acceptable level . figure 6 shows how case temperature rise can be managed by reducing v in . acts as a heat sink thermally . to keep thermal resistance low , extend the ground plane as much as possible , and add thermal vias under and near the lt 8608 to additional ground planes within the circuit board and on the bottom ? side . figure 7 shows the basic guidelines for a layout example that can pass cispr 25 radiated emission test with class 5 limits . thermal considerations for higher ambient temperatures , care should be taken in the layout of the pcb to ensure good heat sinking of the lt 8608 . figure 7 shows the recommended component placement with trace , ground plane , and via locations . the exposed pad on the bottom of the package must be soldered to a ground plane . this ground should be tied to large copper layers below with thermal vias ; these layers will spread heat dissipated by the lt 8608 . placing additional vias can reduce thermal resistance further . the maximum load current should be derated as the ambient temperature approaches the maximum junction rating . power dissipation within the lt 8608 can be estimated by calculating the total power loss from an efficiency measurement and subtracting the inductor loss . the die temperature is calculated by multiplying the lt 8608 power dissipation by the thermal resistance from junction figure 6. case temperature rise vs load current lt 8608 / lt 8608 b rev c 1.00 1.25 1.50 0 5 10 15 20 25 30 v in = 6v 35 40 45 50 case temp rise (c) (5v out) 8608 f06 f sw = 2mhz l = 2.2h v in = 12v v in = 36v i out (a) 0.00 0.25 0.50 0.75
18 for more information www.analog.com 8609s f07 gnd via v in via v out via en/uv via other signal via c out c in c bst c vcc ground plane on layer 2 r t l c in (opt) r1 c ff r2 r4 r3 r pg c ss 1 figure 7. pcb layout ( not to scale ) applications information lt 8608 / lt 8608 b rev c
19 for more information www.analog.com typical applications 3.3 v step down 5 v step down 12 v step down v out 3.3v 1.5a 8608 ta03 v out 5v 1.5a 8608 ta04 v out 12v 1.5a 8608 ta05 lt 8608 / lt 8608 b rev c r3 309k r4 100k c6 10nf v in en/uv sync lt8608 intv cc tr/ss rt c1 0.1f gnd fb pg sw bst v in 3.9v to 42v power good f sw = 2mhz l1 = xfl4020-222me c1 0.1f c2 4.7f c2 4.7f c3 1f c4 22f x7r 1206 c5 10pf l1 2.2h r1 18.2k r2 1m r3 187k r4 100k c6 10nf c3 1f v in en/uv sync lt8608 intv cc tr/ss rt gnd fb pg c4 22f x7r 1206 sw bst v in 5.6v to 42v power good f sw = 2mhz l1 = xfl4020-222me c1 0.1f c2 4.7f c3 1f c4 22f x7r 1210 c5 10pf c5 10pf l1 10h r1 40.2k r2 1m r3 69.8k r4 100k c6 10nf v in en/uv sync l1 2.2h lt8608 intv cc tr/ss rt gnd fb pg sw bst v in 12.7v to 42v r1 18.2k power good f sw = 1mhz l1 = xal4040-103me r2 1m
20 for more information www.analog.com typical applications 1.8 v 2 mhz step - down converter ultralow emi 5 v 1.5 a step - down converter v out 1.8v 1.5a 8608 ta06 p skip m1 nfet v out 5v 1.5a 8608 ta07 lt 8608 / lt 8608 b rev c r3 768k r4 100k c6 10nf v in en/uv sync lt8608 (msop) intv cc tr/ss rt c1 0.1f gnd fb pg sw bst v in 3.1v to 20v (42v transient) power good f sw = 2mhz l1 = xfl4020-222me c1 0.1f c2 4.7f c2 4.7f c3 1f c4 22f x 7r 1206 c5 10pf l1 4.7h r1 60.4k r2 1m r3 187k r4 100k c3 1f c6 10nf l2 bead l3 4.7h c7 4.7f c8 4.7f v in en/uv sync lt8608 (msop) intv cc c4 22f x7r 1206 tr/ss rt gnd fb pg sw bst v in 5.8v to 42v power good f sw = 700khz c5 10pf l1 = xfl4020-472me c2, c4, c7, c8 x7r 1206 l1 2.2h r1 18.2k r2 1m
21 for more information www.analog.com package description please refer to http :// www . linear . com / product / lt 8608 # packaging for the most recent package drawings . msop (mse) 0213 rev i 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev i) lt 8608 / lt 8608 b rev c
22 for more information www.analog.com package description please refer to http :// www . linear . com / product / lt 8608 # packaging for the most recent package drawings . 2.00 0.05 (4 sides) 2.00 sq 0.05 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.55 0.05 bottom view?exposed pad 0.23 ref 0.335 ref 0.335 ref 0.75 0.05 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dc8ma) dfn 0113 rev ? 0.23 0.05 0.45 bsc 0.25 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.90 ref 0.23 ref 0.85 0.05 1.8 ref 1.8 ref 2.60 0.05 package outline 0.45 bsc pin 1 notch r = 0.15 dc8 package 8-lead plastic dfn (2mm 2mm) (reference ltc dwg # 05-08-1939 rev ?) exposed pad variation aa lt 8608 / lt 8608 b rev c
23 for more information www.analog.com information furnished by analog devices is believed to be accurate and reliable . however , no responsibility is assumed by analog devices for its use , nor for any infringements of patents or other rights of third parties that may result from its use . specifications subject to change without notice . no license is granted by implication or otherwise under any patent or patent rights of analog devices . revision history rev date description page number a 12/16 clarified minimum on time to 35 ns clarified condition on feedback voltage line regulation clarified transient response graphs 1 2 7 b 01/18 added dfn package option added h - grade temperature options clarified graphs for msop package option only clarified pin functions for msop and dfn package options clarified operation and applications information section for msop and dfn package options added figure 6 clarified typical applications for msop package option 1-3 2 6 8 10-11, 15-17 18 20 c 05/18 added b version added table to clarify versions modified text in description to add dfn functionality added b version to order information clarified minimum on - time conditions clarified efficiency graphs clarified no - load supply current graphs clarified burst mode operation vs output current graph clarified frequency foldback graph clarified pin functions on sync and tr / ss clarified operation third and fifth paragraph clarified last paragraph to include dfn b version and figure 1 and figure 3 clarified applications information to include dfn b version all 1 1 2 3 4 4 5 6 8 10 11 16 lt 8608 / lt 8608 b rev c
24 for more information www.analog.com d16877 0-5/18(c) www.analog.com ? analog devices, inc. 2016-2018 related parts typical application part number description comments lt 8609 / lt 8609 a 42 v , 2 a /3 a peak , 93% efficiency , 2.2 mhz synchronous micropower step - down dc / dc converter with i q ? =?2.5 a v in ?=?3.2 v ? to ?42 v , v out ( min ) ?=?0.8 v , i q ?=?2.5 a , i sd ?

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